ADVANCE INFORMATION
VDP 313xY
Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions
−default values are initializied at reset
FP Sub-
address
Function
Default
Name
(hex)
(hex)
23
luma/chroma delay adjust. The setting is updated when ’sdt’ reg-
0
LDLY
ister is updated.
bit[5:0]
reserved, set to zero
bit[11:6]
luma delay in clocks,
allowed range is +1...−7
21
Input select:
bit[1:0]
writing to this register will also initialize the
standard
INSEL
VIS
luma selector
VIN1
VIN2
VIN3
VIN4
00
00
01
10
11
bit[2]
chroma selector
CIN1
CIN2
0
CIS
IFC
0
1
bit[4:3]
IF compensation
00
00
01
10
11
off
6 dB/Okt
12 dB/Okt
10 dB/MHz only for SECAM
bit[6:5]
chroma bandwidth selector
01
CBW
00
01
10
11
narrow
normal
broad
wide
bit[7]
0/1 adaptive/fixed SECAM notch filter
0/1 enable luma lowpass filter
hpll speed
FNTCH
LOWP
bit[8]
bit[10:9]
HPLLMD
00
01
10
11
no change
terrestrial
vcr
mixed
bit[11]
status bit, write 0, this bit is set to 1 to indicate
operation complete.
Micronas
43
MICRONAS [ MICRONAS ]
