ADVANCE INFORMATION
VDP 313xY
Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions
−default values are initializied at reset
FP Sub-
address
Function
Default
(hex)
Name
(hex)
Standard Selection
20
Standard select:
bit[2:0] standard
0
STD
0
1
2
3
4
5
6
7
PAL B,G,H,I (50 Hz)
4.433618
3.579545
4.286
4.433618
3.575611
3.582056
4.433618
3.579545
PAL
NTSC M
SECAM
NTSC44
PAL M
PAL N
PAL 60
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
NTSC
SECAM
NTSC44
PALM
PALN
PAL60
NTSCC
NTSC COMB (60 Hz)
bit[3]
0/1 standard modifier
PAL modified to simple PAL
SDTMOD
NTSC modified to compensated NTSC
SECAM modified to monochrome 625
NTSCC modified to monochrome 525
bit[4]
bit[5]
bit[6]
reserved (set to 0)
0/1 2-H comb filter off/on
COMB
SVHS
0/1 S-VHS mode off/on
(2-H comb is switched off)
Option bits allow to suppress parts of the initialization, this can be
used for color standard search:
SDTOPT
bit[7]
no hpll setup
bit[8]
no vertical setup
no acc setup
bit[9]
bit[10]
bit[11]
2-H comb filter set-up only
status bit, normally write 0. After the FP has
switched to a new standard, this bit is set to 1 to
indicate operation complete. Standard is automati-
cally initialized when the insel register is written.
Micronas
41
MICRONAS [ MICRONAS ]
