ADVANCE INFORMATION
VDP 313xY
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
Analog RGB Insertion
4B
4B
32
9
9
8
w v
w v
w/r
bit[7]
bit[0]
0/1
disable/enable analog fast blank
input for RGB inserion
0
0
0
ERGB
0
1
Picture frame overOSD
OSD over picture frame
OSDPRIO
fast blank interface mode
FBMOD
FBFOH1
bit[0]
0
1
internal fast blank 1 from FBLIN1
pin
force internal fast blank 1 signal
to high
bit[1]
bit[2]
0/1
0/1
internal fast blank active high/low
FBPOL
CLMPR
disable/enable clamping
reference for RGB outputs
bit[3]
bit[4]
1
full line MADC measurement
window, disables bit [3] in
address 25
FLMW
FLPOL
0/1
horizontal flyback input active
high/low
bit[6:5]
bit[7]
reserved (set to 0)
0
1
internal fast blank 1 from FBLIN1
pin
force internal fast blank 1 signal
to low
FBFOL1
31
8
w/r
fast blank interface mode 2
0
FBMOD2
FBFOH2
bit[0]
0
internal fast blank 2 from FBLIN2
pin
1
force internal fast blank 2 signal
to high
bit[1]
0
1
internal fast blank 2 from FBLIN2
pin
force internal fast blank 2signal to
low
FBFOL2
bit[2]
bit[3]
fast blank input priority
FBPRIO
FBMON
0
1
FBLIN1>FBLIN2
FBLIN2>FBLIN1
fast blank monitor input select
0
1
monitor connected to FBLIN1 pin
monitor connected to FBLIN2 pin
bit[4]
bit[5]
bit[6]
bit[7]
half contrast switch enable
HCSEN
0/1
HCS disable/enable
0
1
half contrast from HCS pin
force half contrast signal to high
HCSFOH
HCSPOL
0/1
half contrast active high/low at
HCS pin
reserved (set to 0)
Micronas
39
MICRONAS [ MICRONAS ]
