ADVANCE INFORMATION
VDP 313xY
Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions
−default values are initializied at reset
FP Sub-
address
Function
Default
(hex)
Name
(hex)
Color Processing
30
Saturation control
2070
ACC_SAT
bit[11:0]
0...4094 (2070 corresponds to 100% saturation)
4095 disabled (test mode only)
17A
39
bit[10:0]
bit[11]
0...2047 CR-attenuation
1591
o
CR_ATT
0/1
disable/enable CR-attenuation
CR_ATT_ENA
bit[10:0]
bit[11]
0...2047 amplitude killer level (0: killer disabled)
25
0
KILVL
0/1
disable/enable chroma ADC
3A
amplitude killer hysteresis
5
0
KILHY
TINT
DC
DVCO
F8
NTSC tint angle, ±512 = ±π/4
crystal oscillator center frequency adjust, −2048...2047
−720
DVCO
F9
crystal oscillator center frequency adjustment value for line lock
mode,true adjust value is DVCO - ADJUST.
read only
ADJUST
For factory crystal alignment, using standard video signal:
set DVCO = 0, set lock mode, read crystal offset from ADJUST
register and use negative value for initial center frequency adjust-
ment via DVCO.
F7
B5
crystal oscillator line-locked mode, lock command/status
0
XLCK
write: 100
0
read: 0
enable lock
disable lock
unlocked
locked
>2047
crystal oscillator line-locked mode, autolock feature. If autolock is 400
enabled, crystal oscillator locking is started automatically.
AUTOLOCK
bit[11:0]
threshold; 0: autolock off
Micronas
45
MICRONAS [ MICRONAS ]
