ADVANCE INFORMATION
VDP 313xY
Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions
−default values are initializied at reset
FP Sub-
address
Function
Default
Name
(hex)
(hex)
171
bit[11:0]
bit[11:0]
first line of macrovision detection window
(relative to vsync)
6
MCV_START
MCV_STOP
172
last line of macrovision detection window
(relative to vsync)
15
0
Scaler Control Register
40 scaler mode register
SCMODE
MODE
bit[1:0]
scaler mode
0
1
2
3
linear scaling mode
nonlinear scaling mode, ’panorama’
nonlinear scaling mode, ’waterglass’
reserved
bit[10:2]
bit[11]
reserved, set to 0
scaler update
SCUP
0
start scaler update command,
when the registers are updated the bit is set
to 1
41
luma offset register
bit[6:0] luma offset 0..127
57
YOFFS
ITU-R output format:
CVBS output format:
57
4
this register is updated when the scaler mode register is written
active video length for 1-h FIFO
42
43
1080
FFLIM
bit[11:0]
length in pixels
this register is updated when the scaler mode register is written
scaler1 coefficient, this scaler is compressing the signal.
For compression by a factor c the value c*1024 is required.
SCINC1
bit[11:0]
allowed values from 1024..4095
1024
1024
this register is updated when the scaler mode register is written
44
scaler2 coefficient, this scaler is expanding the signal.
For expansion by a factor c the value 1/c*1024 is required.
SCINC2
bit[11:0]
allowed values from 256..1024
this register is updated when the scaler mode register is written
45
scaler1/2 nonlinear scaling coefficient
this register is updated when the scaler mode register is written
0
0
SCINC
47 -
4B
scaler1 window controls, see table
5 12-bit registers for control of the nonlinear scaling
this register is updated when the scaler mode register is written
SCW1_0 - 4
Micronas
47
MICRONAS [ MICRONAS ]
