VDP 313xY
ADVANCE INFORMATION
Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions
−default values are initializied at reset
FP Sub-
address
Function
Default
Name
(hex)
(hex)
148
Enable automatic standard recognition (ASR)
0
ASR_ENA
bit[0]
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
bit[10:7]
bit[11]
0/1 PAL B,G,H,I (50 Hz)
4.433618
3.579545
4.286
0/1 NTSC M
0/1 SECAM
0/1 NTSC44
0/1 PAL M
0/1 PAL N
(60 Hz)
(50 Hz)
(60 Hz)
(60 Hz)
(50 Hz)
(60 Hz)
4.433618
3.575611
3.582056
4.433618
0/1 PAL 60
reserved set to 0
1
reset status information ‘switch’ in asr_status
(cleared automatically)
0: disable recognition; 1: enable recognition
Note: For correct operation don’t change FP reg. 20h and 21h,
while ASR is enabled!
14E
Status of automatic standard recognition
0
ASR_STATUS
VWINERR
bit[0]
1
error of the vertical standard
(neither 50 nor 60 Hz)
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
1
1
1
1
1
detected standard is disabled
search active
DISABLED
BUSY
search terminated, but failed
no color found
FAILED
NOCOLOR
SWITCH
standard has been switched (since last reset
of this flag with bit[11] of asr_enable)
bit[4:0]
00000 all ok
00001 search not started, because vwin error
detected (no input or SECAM L)
00010 search not started, because detected vert.
standard not enabled
0x1x0 search started and still active
01x00 search failed (found standard not correct)
01x10 search failed, (detected color standard not
enabled)
1000 no color found (monochrome input or switch
betw. CVBS/SVHS necessary)
22
picture start position, this register sets the start point of active
video, this can be used e.g. for panning. The setting is updated
when ’sdt’ register is updated.
0
SFIF
42
Micronas
MICRONAS [ MICRONAS ]
