VDP 313xY
ADVANCE INFORMATION
Table 2–6: Control Registers of the Fast Processor for control of the video frontend functions
−default values are initializied at reset
FP Sub-
address
Function
Default
(hex)
Name
(hex)
FP Status Register
12 general purpose control bits
GPC
bit[2:0]
bit[3]
reserved, do not change
vertical standard force
reserved, do not change
disable flywheel interlace
reserved, do not change
0
1
VFRC
DFLW
bit[8:4]
bit[9]
bit[11:10]
to enable vertical free run mode set vfrc to 1 and dflw to 0
13
standard recognition status (see also: ‘automatic standard recog-
nition’)
−
ASR
bit[0]
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
bit[6]
bit[7]
bit[8]
bit[9]
bit[11:10]
1
1
vertical lock
horizontally locked
no signal detected
1
1
1
1
1
1
1
color amplitude killer active
disable amplitude killer
color ident killer active
disable ident killer
interlace detected
no vertical sync detection
spurious vertical sync detection
reserved
14
CB
15
74
input noise level
read only
read only
NOISE
NLPF
number of lines per field, P/S: 312, N: 262
vertical field counter, incremented per field
VCNT
SAMPL
measured sync amplitude value, nominal: 768 (PAL), 732
(NTSC)
read only
36
F0
measured burst amplitude
firmware version number
read only
read only
BAMPL
SW_VERSION
bit[7:0]
internal revision number
firmware release
bit[11:8]
170
status of macrovision detection
read only
MCV_STATUS
bit[0]
bit[1]
AGC pulse detected
pseudo sync detected
46
Micronas
MICRONAS [ MICRONAS ]
