VDP 313xY
ADVANCE INFORMATION
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
PLL2/3 filter coefficients, 1of5 bit code
(n+ set bit number)
62
66
6A
9
9
9
w v
w v
w v
bit[5:0]
bit[5:0]
bit[5:0]
proportional coefficient PLL3, 2−n−1
proportional coefficient PLL2, 2−n−1
integral coefficient PLL2, 2−n−5
2
1
2
PKP3
PKP2
PKI2
15
16
w/r
horizontal drive and vertical signal control register
HVC
bit[5:0]
0..63
horizontal drive pulse duration in 32
HDRV
µs (internally limited to 4..61)
bit[6]
0/1
disable/enable horizontal PLL2
and PLL3
0
0
EHPLL
EFLB
bit[7]
0/1
1: disable horizontal drive pulse
during flyback
bit[8]
bit[9]
0/1
0/1
reserved, set to ’0’
0
0
enable/disable ultra black
blanking
DUBL
EBL
bit[10]
bit[11]
bit[12]
0/1
0/1
0/1
0: all outputs blanked
1: normal mode
1
0
0
enable/disable clamping for
analog RGB input
DCRGB
SELFT
disable/enable vertical free
running mode (FIELD is set to
field2, no interlace)
bit[13]
bit[14]
bit[15]
0/1
enable/disable vertical protection
0
0
1
DVPR
reserved (set to 0)
0/1 disable/enable phase shift of
DISKA
SYCTRL
display clock
9D
8
w/r
sync output control
0
bit[0]
bit[1]
bit[2]
bit[3]
bit[4]
bit[5]
invert INTLC
disable INTLC (tristateINTLC output)
invert VS
disable VS
disable CSY
force INTLC to polarity defined in
’INTLCINV’
9E
8
w/r
delay of CSY output (relative to PLL2)
bit[7:0] −128..127 ± 8 µs
0
CSYDEL
38
Micronas
MICRONAS [ MICRONAS ]
