ADVANCE INFORMATION
VDP 313xY
Table 2–5: I2C control and status registers of the video backend
(Registers are set to ’0’ at reset, default values are recommendations)
I2C Sub
address
Number
of bits
Mode Function
Default Name
(hex)
(hex)
1E
8
r
measurement adc status and fast blank input status
measurement status register
−
PMS
bit[0]
0/1
tube measurement active /
complete
bit[2:1]
white drive measurement cycle
red
green
blue
reserved
00
01
10
11
bit[3]
0/1
picture measurement active /
complete
bit[4]
bit[5]
0/1
1
fast blank input low / high (static)
fast blank input negative transi-
tion since last read (bit reset at
read)
bit[7:6]
reserved
Vertical Timing
67
77
5F
9
9
9
w v
w v
w v
vertical blanking start
bit[8:0] 0..511
VBST
VBSO
VPER
first line of vertical blanking
last line of vertical blanking
305
vertical blanking stop
bit[8:0] 0..511
25
free running field period
309
bit[8:0]
period = (value+4) lines
Horizontal Deflection and Timing
76
7A
6E
9
9
9
w v
w v
w v
linear term of angle & bow correction
0
ANGLE
BOW
bit[8:0]
−256..+255 ± 500 ns
quadratic term of angle & bow correction
bit[8:0] −256..+255 ± 500 ns
0
adjustable delay of PLL2, clamping, and blanking
(relative to front sync)
−141
POFS2
bit[8:0]
−256..+255 ± 8 µs
72
7E
9
9
w v
w v
adjustable delay of horizontal drive & flyback (relative
to PLL2)
0
POFS3
HPOS
bit[8:0]
−256..+255 ± 8 µs
adjustable delay of main sync (relative to PLL2)
adjust horizontal position for digital picture
120
bit[8:0]
20 steps=1 µs
5B
57
9
9
w v
w v
start of horizontal blanking
bit[8:0] 0..511
1
HBST
HBSO
end of horizontal blanking
bit[8:0] 0..511
48
Micronas
37
MICRONAS [ MICRONAS ]
