128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Command Definitions
Command Definitions
Commands are written to the device to control all operations. Some commands are
two-cycle commands that use a SETUP and a CONFIRM command; other commands
are single-cycle commands that use only a SETUP command followed by a data READ
cycle or data WRITE cycle. Valid commands and their associated command codes are
shown in the table below.
The device supports READ-While-WRITE and READ-While-ERASE operations with bus
cycle granularity, not command granularity. That is, both bus WRITE cycles of a two-cy-
cle command do not need to occur as back-to-back bus WRITE cycles to the device;
READ cycles may occur between the two write WRITE cycles of a two-cycle command.
However, a WRITE operation must not occur between the two bus WRITE cycles of a
two-cycle command; this will cause a command sequence error (SR[7,5,4] = 1).
Due to the large buffer size of devices, the system interrupt latency may be impacted
during the buffer fill phase of a buffered programming operation. Please refer to the rel-
evant Application Note to implement a software solution for your system
Figure 6: Two-Cycle Command Sequence
Address
Partition A
Partition A
Partition B
WE#
OE#
D/Q
Setup
Confirm
00FFh
Figure 7: Single-Cycle Command Sequence
Address
Partition A
Partition A
Partition B
WE#
OE#
D/Q
Setup
00FFh
Figure 8: READ Cycle Between WRITE Cycles
Address
Partition A
Partition B
Partition A
WE#
OE#
D/Q
Setup
Read data
Confirm
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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