128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Bus Interface
Write
CE# LOW and WE# LOW place the device in bus write mode, where RST# and OE# must
be HIGH, CLK and ADV# are ignored, input data and address are sampled on the rising
edge of WE# or CE#, whichever occurs first.
During a write operation in muxed devices, address is latched during the rising edge of
ADV# OR CE# whichever occurs first and Data is latched during the rising edge of WE#
OR CE# whichever occurs first.
Bus WRITE cycles are asynchronous only.
The following conditions apply when a bus WRITE cycle occurs immediately before, or
immediately after, a bus READ cycle:
• When transitioning from a bus READ cycle to a bus WRITE cycle, CE# or ADV# must
toggle after OE# goes HIGH.
• When in synchronous read mode (RCR15 = 0; burst clock running), bus WRITE cycle
t
timings tVHWL (ADV# HIGH to WE# LOW), CHWL (CLK HIGH to WE# LOW), and
tWHCH (WE# HIGH to CLK HIGH) must be met.
• When transitioning from a bus WRITE cycle to a bus READ cycle, CE# or ADV# must
toggle after WE# goes HIGH.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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