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PC28F128G18FF 参数 Datasheet PDF下载

PC28F128G18FF图片预览
型号: PC28F128G18FF
PDF下载: 下载PDF文件 查看货源
内容描述: 128MB, 256MB,512MB ,1GB的StrataFlash存储器 [128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory]
分类和应用: 存储
文件页数/大小: 118 页 / 1154 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory  
Bus Interface  
Asynchronous Read  
For RCR15 = 1 (default), CE# LOW and OE# LOW place the device in asynchronous bus  
read mode:  
• RST# and WE# must be held HIGH; CLK must be tied either HIGH or LOW.  
• Address inputs must be held stable throughout the access, or latched with ADV#.  
• ADV# must be held LOW or can be toggled to latch the address.  
• Valid data is output on the data I/Os after tAVQV, tELQV, tVLQV, or tGLQV, whichever is  
satisfied last.  
Asynchronous READ operations are independent of the voltage level on VPP  
.
For asynchronous page reads, subsequent data words are output tAPA after the least sig-  
nificant address bit(s) are toggled: 16-word page buffer, A[3:0].  
Synchronous Read  
For RCR15 = 0, CE# LOW, OE# LOW, and ADV# LOW place the device in synchronous  
bus read mode:  
• RST# and WE# must be held HIGH.  
• CLK must be running.  
• The first data word is output tCHQV after the latency count has been satisfied.  
• For array reads, the next address data is output tCHQV after valid CLK edges until the  
burst length is satisfied.  
• For nonarray reads, the same address data is output tCHQV after valid CLK edges until  
the burst length is satisfied.  
The address for synchronous read operations is latched on the ADV# rising edge or the  
first rising CLK edge after ADV# low, whichever occurs first for devices that support up  
to 108 MHz. For devices that support up to 133 MHz, the address is latched on the last  
CLK edge when ADV# is low.  
Burst Wrapping  
Data stored within the memory array is arranged in rows or word lines. During synchro-  
nous burst reads, data words are sensed in groups from the array. The starting address  
of a synchronous burst read determines which word within the wordgroup is output  
first, and subsequent words are output in sequence until the burst length is satisfied.  
The setting of the burst wrap bit (RCR3) determines whether synchronous burst reads  
will wrap within the wordgroup or continue on to the next wordgroup.  
PDF: 09005aef8448483a  
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
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© 2011 Micron Technology, Inc. All rights reserved.