128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Bus Interface
Figure 3: Main Array Word Lines
16-Word sense group
16-bit data word
0x000030
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
7
7
7
7
8
8
8
8
9
9
9
9
A
A
A
A
B
B
B
B
C
C
C
C
D
D
D
D
E
E
E
E
F
F
F
F
0x000020
0x000010
Word
lines
0x000000
Address
Bit lines
256 bits
Figure 4: Wrap/No-Wrap Example
16-bit data word
2
2
3
3
4
4
5
5
6
6
7
8
8
9
9
A
A
B
B
7
Wrap
No wrap
End-of-Wordline Delay
Output delays may occur when the burst sequence crosses the first end-of-wordline
boundary onto the start of the next wordline.
No delays occur if the starting address is sense-group aligned or if the burst sequence
never crosses a wordline boundary. However, if the starting address is not sense-group
aligned, the worst-case end-of-wordline delay is one clock cycle less than the initial ac-
cess latency count used. This delay occurs only once during the burst access. WAIT in-
forms the system of this delay when it occurs.
Figure 5: End-of-Wordline Delay
0x000020
0x000010
0
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9 A
9 A
B
B
C
C
D
D
E
E
F
F
EOWL delay
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
19
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