128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Bus Interface
Bus Interface
The bus interface uses CMOS-compatible address, data, and bus control signals for all
bus WRITE and bus READ operations. The address signals are input only, the data sig-
nals are input/output (I/O), and the bus control signals are input only. The address in-
puts are used to specify the internal device location during bus READ and bus WRITE
operations. The data I/Os carry commands, data, or status to and from the device. The
control signals are used to select and deselect the device, indicate a bus READ or bus
WRITE operation, synchronize operations, and reset the device.
Do not float any inputs. All inputs must be driven or terminated for proper device oper-
ation. Some features may use additional signals. See Signal Descriptions for descrip-
tions of these signals.
The following table shows the logic levels that must be applied to the bus control signal
inputs for the bus operations listed.
Table 6: Bus Control Signals
X = Don’t Care; High = VIH; Low = VIL
Bus Operations
Reset
RST#
Low
CE#
X
CLK
ADV#
OE#
X
WE#
X
Address
X
Data I/O
High-Z
High-Z
High-Z
Output
Output
Input
X
X
X
Standby
High
High
High
High
High
High
X
X
X
X
X
Output Disable
Asynchronous Read
Synchronous Read
Write
X
X
High
Low
Low
High
X
X
Low
Low
Low
X
Running
X
Low
Toggle
X
High
High
Low
Valid
Valid
Valid
Reset
RST# LOW places the device in reset, where device operations are disabled; inputs are
ignored, and outputs are placed in High-Z.
Any ongoing ERASE or PROGRAM operation will be aborted and data at that location
will be indeterminate.
RST# HIGH enables normal device operations. A minimum delay is required before the
device is able to perform a bus READ or bus WRITE operation. See AC specifications.
Standby
RST# HIGH and CE# HIGH place the device in standby, where all other inputs are ignor-
ed, outputs are placed in High-Z (independent of the level placed on OE#), and power
consumption is substantially reduced.
Any ongoing ERASE or PROGRAM operation continues in the background and the de-
vice draws active current until the operation has finished.
Output Disable
When OE# is deasserted with CE# asserted, the device outputs are disabled. Output pins
are placed in a high-impedance state. WAIT is deasserted in AD-muxed devices and
driven to High-Z in non-multiplexed devices.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
17
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