128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Status Register
Clear Status Register
The status register has status bits and error bits. Status bits are set and cleared by the
device; error bits are only set by the device. Error bits are cleared using the CLEAR STA-
TUS REGISTER command or by resetting the device.
Note: Care should be taken to avoid status register ambiguity. If a command sequence
error occurs while in erase suspend, SR[5:4] will be set, indicating a command sequence
error. When the ERASE operation is resumed (and finishes), any errors that may have
occurred during the ERASE operation will be masked by the command sequence error.
To avoid this situation, clear the status register prior to resuming any suspended ERASE
operation.
The CLEAR STATUS REGISTER command functions independent of the voltage level on
VPP. Issuing the CLEAR STATUS REGISTER command places the addressed partition in
read status register mode. Other partitions are not affected.
Table 9: CLEAR STATUS REGISTER Command Bus Cycles
Setup WRITE Cycle
Address Bus
Device address
Setup WRITE Cycle Confirm WRITE Cycle Confirm WRITE Cycle
Command
Data Bus
Address Bus
Data Bus
CLEAR STATUS
REGISTER
0050h
–
–
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
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