128Mb, 256Mb, 512Mb, 1Gb StrataFlash Memory
Signal Descriptions
Signal Descriptions
Table 4: Signal Descriptions
Symbol
Non-MUX
A[MAX:1]
DQ[15:0]
Type
Description
Input
Address inputs: Address inputs for all READ/WRITE cycles.
Input/Output Data: Data or command inputs during WRITE cycles; data, status, or device informa-
tion outputs during READ cycles.
A/D MUX
A[MAX:17]
ADQ[15:0]
Input
Address inputs: Upper address inputs for all READ/WRITE cycles.
Input/Output Address or data: Lower address inputs during the address phase for all READ/WRITE
cycles; data or command inputs during WRITE cycles; data, status, or device informa-
tion outputs during READ cycles.
Control Signals
CE#
Input
Chip enable: LOW true input. When LOW, CE# selects the die; when HIGH, CE# dese-
lects the die and places it in standby.
OE#
WE#
CLK
Input
Input
Input
Input
Output enable: LOW true input. Must be LOW for READs and HIGH for WRITEs.
Write enable: LOW true input. Must be LOW for WRITEs and HIGH for READs.
Clock: Synchronizes burst READ operations with the host controller.
ADV#
Address valid: LOW true input. When LOW, ADV# enables address inputs. For syn-
chronous burst READs, address inputs are latched on the rising edge.
WP#
RST#
VPP
Input
Input
Write protect: LOW true input. When LOW, WP# enables block lock down; when
HIGH, WP# disables block lock down.
Reset: LOW true input. When LOW, RST# inhibits all operations; must be HIGH for
normal operations.
Input
Erase/program voltage: Enables voltage for PROGRAM and ERASE operations. Array
contents cannot be altered when VPP is at or below VPPLK
.
WAIT
VCC
Output
Power
Power
Power
Power
WAIT: Configurable HIGH or LOW true output. When asserted, WAIT indicates
DQ[15:0] is invalid; when de-asserted, WAIT indicates DQ[15:0] is valid.
Core power: Supply voltage for core circuits. All operations are inhibited when VCC is
at or below VLKO
I/O power: Supply voltage for all I/O drivers. All operations are inhibited when VCCQ is
at or below VLKOQ
.
VCCQ
VSS
.
Logic ground: Core logic ground return. Connect all VSS balls to system ground; do
not float any VSS balls.
VSSQ
I/O ground: I/O driver ground return. Connect all VSSQ balls to system ground; do not
float any VSSQ balls.
PDF: 09005aef8448483a
128_256_512_65nm_g18.pdf - Rev. F 8/11 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
15
© 2011 Micron Technology, Inc. All rights reserved.
MICRON [ MICRON TECHNOLOGY ]
