512Mb, Multiple I/O Serial Flash Memory
XIP Mode
Table 32: Effects of Running XIP in Different Protocols (Continued)
Protocol
Effect
Quad I/O1
Values of DQ[3:1] during the first dummy clock cycle are "Don't Care." In a de-
vice with a dedicated part number, it is only possible to reset memory when the
device is deselected.
1. In a device with a dedicated part number where RST# is enabled, a LOW pulse on that
pin resets XIP and the device to the state it was in previous to the last power-up, as de-
fined by the nonvolatile configuration register only when the device is deselected.
Note:
Terminating XIP After a Controller and Memory Reset
The system controller and the device can become out of synchronization if, during the
life of the application, the system controller is reset without the device being reset. In
such a case, the controller can reset the memory to power-on reset if the memory has
reset functionality. (Reset is available in devices with a dedicated part number.)
• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)
These sequences cause the controller to set the XIP confirmation bit to 1, thereby termi-
nating XIP. However, it does not reset the device or interrupt PROGRAM/ERASE opera-
tions that may be in progress. After terminating XIP, the controller must execute RESET
ENABLE and RESET MEMORY to implement a software reset and reset the device.
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