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N25Q512A13GF840E 参数 Datasheet PDF下载

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型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Power-Up and Power-Down  
Table 33: Power-Up Timing and VWI Threshold  
Note 1 applies to entire table  
Symbol  
tVTR  
tVTW  
Parameter  
Min  
Max  
150  
150  
2.5  
Unit  
µs  
VCC,min to read  
VCC,min to device fully accessible  
Write inhibit voltage  
µs  
VWI  
tVTP  
1.5  
V
VCC,min to polling allowed  
100  
µs  
1. Parameters listed are characterized only.  
Note:  
Power Loss Recovery Sequence  
If a power loss occurs during a WRITE NONVOLATILE CONFIGURATION REGISTER  
command, after the next power-on, the device might begin in an undetermined state  
(XIP mode or an unnecessary protocol). If this occurs, until the next power-up, a recov-  
ery sequence must reset the device to a fixed state (extended SPI protocol without XIP).  
After the recovery sequence, the issue should be resolved definitively by running the  
WRITE NONVOLATILE CONFIGURATION REGISTER command again. The recovery se-  
quence is composed of two parts that must be run in the correct order. During the en-  
tire sequence, tSHSL2 must be at least 50ns. The first part of the sequence is DQ0 (PAD  
DATA) and DQ3 (PAD HOLD) equal to 1 for the situations listed below:  
• 7 clock cycles within S# LOW (S# becomes HIGH before 8th clock cycle)  
• + 9 clock cycles within S# LOW (S# becomes HIGH before 10th clock cycle)  
• + 13 clock cycles within S# LOW (S# becomes HIGH before 14th clock cycle)  
• + 17 clock cycles within S# LOW (S# becomes HIGH before 18th clock cycle)  
• + 25 clock cycles within S# LOW (S# becomes HIGH before 26th clock cycle)  
• + 33 clock cycles within S# LOW (S# becomes HIGH before 34th clock cycle)  
The second part of the sequence is exiting from dual or quad SPI protocol by using the  
following FFh sequence: DQ0 and DQ3 equal to 1 for 8 clock cycles within S# LOW; S#  
becomes HIGH before 9th clock cycle.  
After this two-part sequence the extended SPI protocol is active.  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
75  
© 2011 Micron Technology, Inc. All rights reserved.  
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