512Mb, Multiple I/O Serial Flash Memory
AC Reset Specifications
Figure 39: Reset AC Timing During PROGRAM or ERASE Cycle
S#
t
t
SHRH
RHSL
t
RLRH
RESET#
Don’t Care
Figure 40: Reset Enable
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
C
S#
tSHSL2
tSHSL3
Reset enable
Reset memory
DQ0
Figure 41: Serial Input Timing
tSHSL
S#
tCHSL
tSLCH
tCHSH
tSHCH
C
tCHCL
tDVCH t
CHDX
tCLCH
LSB in
DQ0
DQ1
MSB in
High-Z
High-Z
Don’t Care
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
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