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N25Q512A13GF840E 参数 Datasheet PDF下载

N25Q512A13GF840E图片预览
型号: N25Q512A13GF840E
PDF下载: 下载PDF文件 查看货源
内容描述: 美光的串行NOR闪存3V ,多个I / O, 4KB扇区擦除N25Q512A [Micron Serial NOR Flash Memory 3V, Multiple I/O, 4KB Sector Erase N25Q512A]
分类和应用: 闪存
文件页数/大小: 91 页 / 1214 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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512Mb, Multiple I/O Serial Flash Memory  
Power-Up and Power-Down  
Power-Up and Power-Down  
Power-Up and Power-Down Requirements  
At power-up and power-down, the device must not be selected; that is, S# must follow  
the voltage applied on VCC until VCC reaches the correct values: VCC,min at power-up and  
VSS at power-down.  
To avoid data corruption and inadvertent WRITE operations during power-up, a power-  
on reset circuit is included. The logic inside the device is held to RESET while VCC is less  
than the power-on reset threshold voltage shown here; all operations are disabled, and  
the device does not respond to any instruction. During a standard power-up phase, the  
device ignores all commands except READ STATUS REGISTER and READ FLAG STATUS  
REGISTER. These operations can be used to check the memory internal state. After  
power-up, the device is in standby power mode; the write enable latch bit is reset; the  
write in progress bit is reset; and the lock registers are configured as: (write lock bit, lock  
down bit) = (0,0).  
Normal precautions must be taken for supply line decoupling to stabilize the VCC sup-  
ply. Each device in a system should have the VCC line decoupled by a suitable capacitor  
(typically 100nF) close to the package pins. At power-down, when VCC drops from the  
operating voltage to below the power-on-reset threshold voltage shown here, all opera-  
tions are disabled and the device does not respond to any command.  
When the operation is in progress, the program or erase controller bit of the status reg-  
ister is set to 0. To obtain the operation status, the flag status register must be polled  
twice, with S# toggled twice in between commands. When the operation completes, the  
program or erase controller bit is cleared to 1. The cycle is complete after the flag status  
register outputs the program or erase controller bit to 1 both times.  
Note: If power-down occurs while a WRITE, PROGRAM, or ERASE cycle is in progress,  
data corruption may result.  
VPPH must be applied only when VCC is stable and in the VCC,min to VCC,max voltage  
range.  
Figure 38: Power-Up Timing  
VCC  
VCC,max  
Chip selection not allowed  
tVTW = tVTR  
Device fully accessible  
VCC,min  
VWI  
t
Chip reset  
VTP  
Polling allowed  
SPI protocol  
Starting protocol defined by NVCR  
WIP = 1  
WEL = 0  
WIP = 0  
WEL = 0  
Time  
PDF: 09005aef84752721  
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
74  
© 2011 Micron Technology, Inc. All rights reserved.  
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