512Mb, Multiple I/O Serial Flash Memory
READ MEMORY Operations
Table 25: Command/Address/Data Lines for READ MEMORY Commands (Continued)
Note 1 applies to entire table
Command Name
DUAL
QUAD
FAST
DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT
READ
READ
FAST READ
FAST READ
FAST READ
FAST READ
STR Mode
DTR Mode
Data Output
03
–
0B
0D
3B
3D
–
BB
BD
–
6B
EB
6D
ED
–
DQ[3:0]
DQ[3:0]
DQ[3:0]
1. Yes in the "Supported' row for each protocol indicates that the command in that col-
umn is supported; when supported, a command's functionality is identical for the entire
column regardless of the protocol. For example, a FAST READ functions the same for all
three protocols even though its data is input/output differently depending on the pro-
tocol.
Notes:
2. FAST READ is similar to READ, but requires dummy clock cycles following the address
bytes and can operate at a higher frequency (fC).
4-Byte Address
To execute 4-byte READ MEMORY commands, S# is driven LOW. The command code is
input on DQn, followed by input on DQn of four address bytes. Each address bit is
latched in during the rising edge of the clock. The addressed byte can be at any location,
and the address automatically increments to the next address after each byte of data is
shifted out; therefore, a die can be read with a single command. The operation is termi-
nated by driving S# HIGH at any time during data output.
Table 26: Command/Address/Data Lines for READ MEMORY Commands – 4-Byte Address
Notes 1 and 2 apply to entire table
Command Name (4-Byte Address)
DUAL
QUAD
FAST
DUAL OUTPUT INPUT/OUTPUT QUAD OUTPUT INPUT/OUTPUT
READ
03/13
–
READ
FAST READ
FAST READ
FAST READ
FAST READ
STR Mode
0B/0C
0D
3B/3C
BB/BC
6B/6C
EB/EC
DTR Mode
3D
BD
6D
ED
Extended SPI Protocol
Supported
Yes
Yes
Yes
DQ0
Yes
Yes
DQ0
Yes
Command Input
Address Input
Data Output
DQ0
DQ0
DQ1
DQ0
DQ0
DQ1
DQ0
DQ0
DQ0
DQ[1:0]
DQ[1:0]
DQ0
DQ[3:0]
DQ[3:0]
DQ[1:0]
DQ[3:0]
Dual SPI Protocol
Supported
No
–
Yes
Yes
Yes
No
–
No
–
Command Input
Address Input
Data Output
DQ[1:0]
DQ[1:0]
DQ[1:0]
DQ[1:0]
DQ[1:0]
DQ[1:0]
DQ[1:0]
DQ[1:0]
DQ[1:0]
–
–
–
–
–
–
PDF: 09005aef84752721
n25q_512mb_1ce_3V_65nm.pdf - Rev. O 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
45
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