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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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N25Q128 - 1.8 V  
Instructions  
Figure 24. Quad Input Extended Fast Program instruction sequence  
S
C
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15  
16  
18 19  
17  
20 21  
22  
23  
24 25 26 27  
Data In  
Data In  
Data In  
Instruction  
24-bit address  
2
5
7
1
3
4
6
4
4
4
0
4
8
0
20 16 12  
4
0
0
0
4
0
4
0
4
0
DQ0  
DQ1  
DQ2  
Don’t Care  
Don’t Care  
9
5
6
5
6
5
6
1
2
5
6
21 17 13  
22 18 14  
1
2
1
2
5
6
1
2
1
2
1
2
5
6
5
6
1
2
5
6
1
2
10  
11  
DQ3  
7
7
7
3
7
3
7
3
3
3
7
3
23 19 15  
7
3
7
3
‘1’  
MSB  
MSB MSB  
MSB  
MSB  
MSB  
MSB  
Quad_Input_Extended_Fast_Program  
9.1.16  
Program OTP instruction (POTP)  
The Program OTP instruction (POTP) is used to program at most 64 bytes to the OTP  
memory area (by changing bits from 1 to 0, only). Before it can be accepted, a Write Enable  
(WREN) instruction must previously have been executed. After the Write Enable (WREN)  
instruction has been decoded, the device sets the Write Enable Latch (WEL) bit.  
The Program OTP instruction is entered by driving Chip Select (S) Low, followed by the  
instruction opcode, three address bytes and at least one data byte on Serial Data input  
(DQ0). Chip Select (S) must be driven High after the eighth bit of the last data byte has been  
latched in, otherwise the Program OTP instruction is not executed.  
There is no rollover mechanism with the Program OTP (POTP) instruction. This means that  
the Program OTP (POTP) instruction must be sent with a maximum of 65 bytes to program,  
once all 65 bytes have been latched in, any following byte will be discarded.  
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose  
duration is tPP) is initiated. While the Program OTP cycle is in progress, the Status Register  
may be read to check the value of the Write In Progress (WIP) bit. The Write In Progress  
(WIP) bit is 1 during the self-timed Program OTP cycle, and it is 0 when it is completed. At  
some unspecified time before the cycle is complete, the Write Enable Latch (WEL) bit is  
reset.  
To lock the OTP memory:  
Bit 0 of the OTP control byte, that is byte 64, is used to permanently lock the OTP memory  
array.  
„
„
When bit 0 of byte 64 = '1', the 64 bytes of the OTP memory array can be programmed.  
When bit 0 of byte 64 = '0', the 64 bytes of the OTP memory array are read-only and  
cannot be programmed anymore.  
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