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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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N25Q128 - 1.8 V  
Instructions  
9.1.13  
Dual Input Extended Fast Program  
The Dual Input Extended Fast Program (DIEFP) instruction is very similar to the Dual Input  
Fast Program (DIFP), except that the address bits are shifted in on two pins (pin DQ0 and  
pin DQ1) instead of only one.  
Figure 22. Dual Input Extended Fast Program instruction sequence  
S
Mode 3  
Mode 0  
0
1
2
3
4
5
6
7
8
9
10 11 12  
14 15 16  
18 19 20  
13  
17  
C
Instruction  
6
4
2
3
0
1
DQ0  
DQ1  
6
7
4
5
2
3
0
1
6
7
4
5
2
3
0
1
7
5
Address  
Dummy Cycles  
S
33 34  
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32  
35  
C
6
4
2
0
DQ0  
DQ1  
6
7
4
2
0
6
7
4
2
0
6
7
4
2
0
1
6
7
4
2
0
Data In 1  
Data In 256  
Data In 2  
Data In 4  
Data In 3  
7
5
3
1
5
3
1
5
3
1
5
3
5
1
3
MSB  
MSB  
MSB  
MSB  
MSB  
Dual_Input_Extended_Fast_Program  
9.1.14  
Quad Input Fast Program  
The Quad Input Fast Program (QIFP) instruction is very similar to the Dual Input Fast  
Program (DIFP) instruction, except that the data are entered on four pins (pin DQ0, pin  
DQ1, pin W/VPP/DQ2 and pin HOLD/ (DQ3) instead of only two. Inputting the data on four  
pins instead of two doubles the data transfer bandwidth compared to the Dual Input Fast  
Program (DIFP) instruction.  
The Quad Input Fast Program (QIFP) instruction is entered by driving Chip Select (S) Low,  
followed by the instruction code, three address bytes and at least one data byte on Serial  
Data input (DQ0).  
If the 8 least significant address bits (A7-A0) are not all zero, all transmitted data that goes  
beyond the end of the current page are programmed from the start address of the same  
page (from the address whose 8 least significant bits (A7-A0) are all zero). Chip Select (S)  
must be driven Low for the entire duration of the sequence.  
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