欢迎访问ic37.com |
会员登录 免费注册
发布采购

N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号N25Q128A11B1241F的Datasheet PDF文件第90页浏览型号N25Q128A11B1241F的Datasheet PDF文件第91页浏览型号N25Q128A11B1241F的Datasheet PDF文件第92页浏览型号N25Q128A11B1241F的Datasheet PDF文件第93页浏览型号N25Q128A11B1241F的Datasheet PDF文件第95页浏览型号N25Q128A11B1241F的Datasheet PDF文件第96页浏览型号N25Q128A11B1241F的Datasheet PDF文件第97页浏览型号N25Q128A11B1241F的Datasheet PDF文件第98页  
Instructions  
N25Q128 - 1.8 V  
If more than 256 bytes are sent to the device, previously latched data are discarded and the  
last 256 data bytes are guaranteed to be programmed correctly within the same page. If less  
than 256 data bytes are sent to device, they are correctly programmed at the requested  
addresses without having any effects on the other bytes in the same page.  
For optimized timings, it is recommended to use the Quad Input Fast Program (QIFP)  
instruction to program all consecutive targeted bytes in a single sequence rather to using  
several Quad Input Fast Program (QIFP) sequences each containing only a few bytes See  
Table 33.: AC Characteristics.  
Chip Select (S) must be driven High after the eighth bit of the last data byte has been  
latched in, otherwise the Quad Input Fast Program (QIFP) instruction is not executed.  
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose  
duration is tPP) is initiated. While the Quad Input Fast Program (QIFP) cycle is in progress,  
the Status Register may be read to check the value of the Write In Progress (WIP) bit. The  
Write In Progress (WIP) bit is 1 during the self-timed Page Program cycle, and 0 when it is  
completed. At some unspecified time before the cycle is completed, the Write Enable Latch  
(WEL) bit is reset.  
A Quad Input Fast Program (QIFP) instruction applied to a page that is protected by the  
Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed.  
A Quad Input Fast Program cycle can be paused by mean of Program/Erase Suspend  
(PES) instruction and resumed by mean of Program/Erase Resume (PER) instruction.  
Figure 23. Quad Input Fast Program instruction sequence  
S
C
0
1
2
3
4
5
6
7
8
9
10  
34 35 36 37 38 39  
41 42 43  
40  
28 29 30 31 32 33  
Data In  
6
Data In  
Data In  
3
4
Instruction  
24-bit address  
1
2
5
4
5
6
7
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
23 22 21  
0
1
2
3
0
1
2
3
3
2
0
0
1
2
3
4
5
6
7
DQ0  
DQ1  
1
0
1
2
3
4
5
6
7
0
1
2
3
Don’t Care  
Don’t Care  
Don’t Care  
DQ2  
DQ3  
‘1’  
MSB MSB  
MSB  
MSB  
MSB  
MSB  
Quad_Input_Fast_Program  
9.1.15  
Quad Input Extended Fast Program  
The Quad Input Extended Fast Program (QIEFP) instruction is very similar to the Quad  
Input Extended Fast Program (QIFP), except that the address bits are shifted in on four pins  
(pin DQ0, pin DQ1, pin W/VPP/DQ2 and pin HOLD/DQ3) instead of only one.  
94/185  
 复制成功!