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N25Q128A11B1241F 参数 Datasheet PDF下载

N25Q128A11B1241F图片预览
型号: N25Q128A11B1241F
PDF下载: 下载PDF文件 查看货源
内容描述: 128兆位, 1.8 V ,多个I / O , 4 KB的界别分组擦除引导扇区, XIP启用,串行闪存与108 MHz的SPI总线接口 [128-Mbit, 1.8 V, multiple I/O, 4-Kbyte subsector erase on boot sectors, XiP enabled, serial flash memory with 108 MHz SPI bus interface]
分类和应用: 闪存
文件页数/大小: 185 页 / 5874 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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Instructions  
N25Q128 - 1.8 V  
several Dual Input Fast Program (DIFP) sequences each containing only a few bytes. See  
Table 33.: AC Characteristics.  
Chip Select (S) must be driven High after the eighth bit of the last data byte has been  
latched in, otherwise the Dual Input Fast Program (DIFP) instruction is not executed.  
As soon as Chip Select (S) is driven High, the self-timed Page Program cycle (whose  
duration is top) is initiated. While the Dual Input Fast Program (DIFP) cycle is in progress,  
the Status Register and the Flag Status Register may be read to check if the internal modify  
cycle is finished. At some unspecified time before the cycle is completed, the Write Enable  
Latch (WEL) bit is reset.  
A Dual Input Fast Program (DIFP) instruction applied to a page that is protected by the  
Block Protect (BP3, BP2, BP1, BP0 and TB) bits is not executed.  
Dual Input Fast Program cycle can be paused by mean of Program/Erase Suspend (PES)  
instruction and resumed by mean of Program/Erase Resume (PER) instruction.  
Figure 21. Dual Input Fast Program instruction sequence  
S
C
0
1
2
3
4
5
6
7
8
9
10  
28 29 30 31  
Instruction  
24-bit address  
23 22 21  
3
2
1
0
DQ0  
DQ1  
High Impedance  
S
C
32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47  
6
4
0
6
4
2
0
1
6
4
0
1
6
4
2
0
1
6
4
0
1
6
4
2
0
1
2
2
2
DQ0  
DQ1  
DATA IN 1  
DATA IN 2  
DATA IN 3  
DATA IN 4  
DATA IN 5  
DATA IN 256  
7
5
3
7
7
5
3
7
5
3
5
3
7
5
1
7
5
3
3
MSB  
MSB  
MSB  
MSB  
MSB  
MSB  
AI14229  
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