‡
Pre lim in a ry
MT9V012 - 1/6-In ch VGA CMOS Dig it a l Im a g e Se n so r
Tw o -Wire Se ria l In t e rfa ce
Sla ve Ad d re ss
The 8-bit address of a two-wire serial interface device consists of 7 bits of address and 1
bit of direction. A “0” in the LSB of the address indicates write mode, and a “1” indicates
read mode. The default slave addresses used by the MT9V012 are 0xBA (write address)
and 0xBB (read address). Reg0x0D[10] can be used to select the alternate slave addresses
0x90 (write address) and 0x91 (read address).
Writes to Reg0x0D[10] are inhibited when STANDBY is asserted (all other writes proceed
normally). This allows two sensors to co-exist as slaves on this interface, but they must
be addressed independently. Enable this capability as follows:
• After RESET# is negated, both sensors will use the default slave address. Reads or
writes on the serial register interface to the default slave address will be decoded by
both sensors simultaneously.
• After reset, assert STANDBY to one sensor and negate STANDBY to the other sensor.
Perform a write to Reg0x0D with bit 10 set. The sensor with STANDBY asserted will
ignore the write to bit 10 and will continue to decode at the default slave address. The
sensor with STANDBY negated will have its Reg0x0D[10] set and will respond to the
alternate slave address for all subsequent READ and WRITE operations.
Da t a Bit Tra n sfe r
Ackn o w le d g e Bit
One data bit is transferred during each clock pulse. The serial interface clock pulse is
provided by the master. The data must be stable during the high period of the two-wire
serial interface clock—it can only change when the serial clock is LOW. Data is trans-
ferred 8 bits at a time, followed by an acknowledge bit.
The master generates the acknowledge clock pulse. The transmitter (which is the master
when writing, or the slave when reading) releases the data line, and the receiver indi-
cates an acknowledge bit by driving the data line LOW during the acknowledge clock
pulse.
No -Ackn o w le d g e Bit
The no-acknowledge bit is generated when the data line is not driven LOW by the
receiver during the acknowledge clock pulse. A no-acknowledge bit is used to terminate
a read sequence.
Pa g e Re g ist e r
The MT9V012 two-wire serial interface and its associated protocols support an address
space of 256 16-bit locations. This address space can be extended by a 3-bit page prefix,
and controlled through accesses to Reg0xF0.
The paging mechanism is intended to allow access to other sets of registers when the
sensor is embedded as part of a more complex integrated sub-system (for example, in an
SOC). All of the registers within the MT9V012 are accessible on page 0 (the default page).
PDF: 814eb99f/Source: 8175e929
MT9V012_2.fm - Rev. B 2/05 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
16
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