64Mb : x4, x8, x16
SDRAM
NOTES
1. All voltages referenced to VSS.
13. IDD specifications are tested after the device is prop-
erly initialized.
14. Tim ing actually specified by CKS; clock(s) speci-
2. This param eter is sam pled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3. IDD is dependent on output loading and cycle rates.
Specified values are obtained with m inim um cycle
tim e and the outputs open.
4. Enables on-chip refresh and address counters.
5. The m in im um specification s are used on ly to
indicate cycle tim e at which proper operation over
the full tem perature range (0°C £ TA £ +70°C and
-40°C £ TA £ +85°C for IT parts) is ensured.
6. An initial pause of 100µs is required after power-
up, followed by two AUTO REFRESH com m ands,
before proper device operation is ensured. (VDD
and VDDQ m ust be powered up sim ultaneously. VSS
and VSSQ m ust be at sam e potential.) The two
AUTO REFRESH com m and wake-ups should be
repeated any tim e the REF refresh requirem ent is
exceeded.
7. AC characteristics assum e T = 1ns.
8. In addition to m eeting the transition rate specifi-
cation, the clock and CKE m ust transit between VIH
and VIL (or between VIL and VIH) in a m onotonic
m an n er.
t
fied as a reference only at m inim um cycle rate.
t
t
15. Tim ing actually specified by WR plus RP; clock(s)
specified as a reference only at m inim um cycle rate.
t
16. Tim ing actually specified by WR.
17. Required clocks are specified by JEDEC function-
ality and are not dependent on any tim ing param -
eter.
18. The IDD current will increase or decrease propor-
tionally according to the am ount of frequency al-
teration for the test condition.
19. Address transitions average one transition every
two clocks.
20. CLK m ust be toggled a m inim um of two tim es dur-
ing this period.
t
t
21. Based on tCK = 10ns for -8E , CK=7.5ns for -75
t
and -7E, CK = 6ns for -6.
t
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse
width £ 3ns, and the pulse width cannot be greater
than one third of the cycle rate. VIL undershoot: VIL
(MIN) = -2V for a pulse width £ 3ns.
23. The clock frequency m ust rem ain constant (stable
clock is defined as a signal cycling within tim ing
constraints specified for the clock pin) during ac-
cess or precharge states (READ, WRITE, including
tWR, and PRECHARGE com m ands). CKE m ay be
used to reduce the data rate.
9. Outputs m easured at 1.5V with equivalent load:
Q
50pF
24. Auto precharge m ode only. The precharge tim ing
budget (tRP) begins 6ns/ 7ns/ 7.5ns/ 7ns after the
first clock delay, after the last WRITE is executed.
25. Precharge m ode only.
t
10. HZ defines the tim e at which the output achieves
the open circuit condition; it is not a reference to
VOH or VOL. The last valid data elem ent will m eet
tOH before going High-Z.
26. JEDEC and PC100 specify three clocks.
t
27. AC for -75/ -7E at CL = 3 with no load is 4.6ns and is
11. AC tim ing and IDD tests have VIL = 0V and VIH = 3V,
with tim ing referenced to 1.5V crossover point. If
the input transition tim e is longer than 1 ns, then
the tim ing is referenced at VIL (MAX) and VIH (MIN)
and no longer at the 1.5V crossover point. CLK
should always be 1.5V referenced to crossover. Re-
fer to Micron Technical Note TN-48-09
12. Other input signals are allowed to transition no
m ore than once every two clocks and are otherwise
at valid VIH or VIL levels.
guaranteed by design.
28. Param eter guaranteed by design.
29. PC100 specifies a m axim um of 4pF.
30. PC100 specifies a m axim um of 5pF.
31. PC100 specifies a m axim um of 6.5pF.
t
32. For -8E, CL = 2 and CK = 10ns; for -75, CL = 3 and
tCK = 7.5ns; for -7E, CL = 2 and CK = 7.5ns; for -6,
t
t
CL = 3 and CK = 6ns.
33. CKE is HIGH durin g refresh com m an d period
tRFC (MIN) else CKE is LOW. The IDD6 lim it is actu-
ally a nom inal value and does not result in a fail
valu e.
64Mb: x4, x8, x16 SDRAM
64MSDRAM_F.p65 – Rev. F; Pub. 1/03
Micron Technology, Inc., reservesthe right to change productsor specificationswithout notice.
©2003, Micron Technology, Inc.
35
MICRON [ MICRON TECHNOLOGY ]
