256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
istered. The last valid data WRITE to bank n will be data registered one clock prior to a
WRITE to bank m (see Figure 47 (page 74)).
Figure 40: READ With Auto Precharge Interrupted by a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
Bank n
READ - AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
Command
Bank n
Page active
READ with burst of 4
Interrupt burst, precharge
Idle
t
t
RP - bank m
RP - bank n
Internal
states
Precharge
Page active
READ with burst of 4
Bank m
Bank n,
Col a
Bank m,
Col d
Address
DQ
D
D
D
D
OUT
OUT
OUT
OUT
CL = 3 (bank n)
CL = 3 (bank m)
Don’t Care
1. DQM is LOW.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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68
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