256Mb: x4, x8, x16 SDRAM
WRITE Operation
Figure 39: WRITE – DQM Operation
T0
T1
T2
T3
T4
T5
T6
T7
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
Command
DQM
ACTIVE
NOP
WRITE
t
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
t
t
t
t
AH
AS
Address
Row
t
Column m
AS
AH
Enable auto precharge
Row
t
A10
Disable auto precharge
Bank
AS
AH
BA0, BA1
Bank
t
t
t
t
t
t
DS
DH
DIN
DS
DH
DS
DH
DIN
DIN
DQ
t
Don’t Care
RCD
1. For this example, BL = 4.
Note:
Burst Read/Single Write
The burst read/single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a 1. In this mode, all WRITE commands result in the access
of a single column location (burst of one), regardless of the programmed burst length.
READ commands access columns according to the programmed burst length and se-
quence, just as in the normal mode of operation (M9 = 0).
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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