256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
Figure 41: READ With Auto Precharge Interrupted by a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
READ - AP
Bank n
WRITE - AP
Bank m
NOP
NOP
NOP
NOP
NOP
NOP
Command
Bank n
Page
active
READ with burst of 4
Page active
Interrupt burst, precharge
t
Idle
Internal
States
t
RP - bank
n
WR - bankm
Write-back
WRITE with burst of 4
Bank m
Address
Bank n,
Col a
Bank m,
Col d
1
DQM
D
D
D
D
D
IN
OUT
IN
IN
IN
DQ
CL = 3 (bank n)
Transitioning data
Don’t Care
1. DQM is HIGH at T2 to prevent DOUTa + 1 from contending with DINd at T4.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 1999 Micron Technology, Inc. All rights reserved.
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