256Mb: x4, x8, x16 SDRAM
WRITE Operation
Figure 37: Alternating Bank Write Accesses
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
t
t
CL
CK
CLK
CKE
t
CH
t
t
CKS
CKH
t
t
CMS
CMH
Command
DQM
ACTIVE
NOP
WRITE
NOP
ACTIVE
NOP
WRITE
NOP
NOP
ACTIVE
t
t
CMS
CMH
t
t
AH
AS
Row
Row
Row
Row
Row
Column m
Column b
Address
t
t
AH
AS
Enable auto precharge
Enable auto precharge
Row
A10
t
t
AH
AS
BA0, BA1
Bank 0
Bank 0
Bank 1
t
Bank 1
Bank 0
t
t
DS
t
t
t
t
t
t
t
t
DS
t
t
t
t
t
DS DH
DS
DS
DS
DS
DS
DH
DIN
WR - bank 0
DH
DH
DH
DH
DH
DH
DIN
DIN
DIN
DIN
DIN
DIN
RP - bank 0
DIN
DQ
t
t
RCD - bank 0
t
t
RCD - bank 0
t
t
t
RAS - bank 0
RC - bank 0
RRD
t
WR - bank 1
t
RCD - bank 1
Don’t Care
1. For this example, BL = 4.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
64
© 1999 Micron Technology, Inc. All rights reserved.
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