256Mb: x4, x8, x16 SDRAM
PRECHARGE Operation
Figure 43: READ Without Auto Precharge
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
Command
ACTIVE
NOP
READ
NOP
NOP
NOP
PRECHARGE
NOP
ACTIVE
t
t
CMS CMH
DQM
t
AS
t
AH
Row
Row
Column m
Address
t
AS
t
AH
All banks
Row
Row
A10
Single bank
Disable auto precharge
Bank
t
t
AS
AH
BA0, BA1
Bank(s)
t
Bank
Bank
t
t
AC
AC
AC
t
t
OH
t
OH
t
OH
t
OH
AC
DOUT
DOUT
DOUT
DOUT
DQ
t
LZ
t
HZ
t
t
RCD
CL = 2
RP
t
RAS
t
RC
Don’t Care
Undefined
1. For this example, BL = 4, CL = 2, and the READ burst is followed by a manual PRE-
CHARGE.
Note:
PDF: 09005aef8091e6d1
256Mb_sdr.pdf - Rev. R 10/12 EN
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