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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
 浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第21页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第22页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第23页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第24页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第26页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第27页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第28页浏览型号MT48LC4M16A2P-75G的Datasheet PDF文件第29页  
64Mb: x4, x8, x16 SDRAM  
Electrical Specifications – AC Operating Conditions  
Table 13: AC Functional Characteristics  
Notes 1–6 apply to all parameters and conditions  
Note  
Parameter  
Symbol -6/-6A  
-7E  
1
-75  
1
Unit  
tCK  
tCK  
tCK  
tCK  
tCK  
s
Last data-in to burst STOP command  
READ/WRITE command to READ/WRITE command  
Last data-in to new READ/WRITE command  
CKE to clock disable or power-down entry mode  
Data-in to ACTIVE command  
tBDL  
tCCD  
tCDL  
1
1
1
1
5
17  
17  
17  
18  
1
1
1
1
tCKED  
tDAL  
1
1
4
5
19,  
20  
Data-in to PRECHARGE command  
tDPL  
2
2
2
tCK  
20,  
21  
DQM to input data delay  
tDQD  
tDQM  
tDQZ  
tDWD  
tMRD  
tPED  
0
0
2
0
2
1
2
0
0
2
0
2
1
2
0
0
2
0
2
1
2
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
tCK  
17  
17  
17  
17  
22  
17  
DQM to data mask during WRITEs  
DQM to data High-Z during READs  
WRITE command to input data delay  
LOAD MODE REGISTER command to ACTIVE or REFRESH command  
CKE to clock enable or power-down exit setup mode  
Last data-in to PRECHARGE command  
tRDL  
20,  
21  
Data-out High-Z from PRECHARGE command  
CL = 3  
CL = 2  
CL = 1  
tROH(3)  
tROH(2)  
tROH(1)  
3
2
1
3
2
3
2
tCK  
tCK  
tCK  
17  
17  
17  
1. Minimum specifications are used only to indicate cycle time at which proper operation  
over the full temperature range is ensured:  
0°C TA +70°C (commercial)  
Notes:  
–40°C TA +85°C (industrial)  
–40°C TA +105°C (automotive)  
2. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH  
commands, before proper device operation is ensured. (VDD and VDDQ must be powered  
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH  
command wake-ups should be repeated any time the tREF refresh requirement is excee-  
ded.  
3. In addition to meeting the transition rate specification, the clock and CKE must transit  
between VIH and VIL (or between VIL and VIH) in a monotonic manner.  
4. Outputs measured at 1.5V with equivalent load:  
Q
50pF  
5. AC operating and IDD test conditions have VIL = 0V and VIH = 3.0V using a measurement  
reference level of 1.5V. If the input transition time is longer than 1ns, then the timing is  
measured from VIL,max and VIH,min and no longer from the 1.5V midpoint. CLK should al-  
ways be 1.5V referenced to crossover. Refer to Micron technical note TN-48-09.  
6. The -6A speed grade is not backward compatible with -7E at CL = 2.  
7. Not applicable for Revision G.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
25  
© 1999 Micron Technology, Inc. All rights reserved.  
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