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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Commands  
Commands  
The following table provides a quick reference of available commands, followed by a  
written description of each command. Additional Truth Tables (Table 15 (page 34), Ta-  
ble 16 (page 36), and Table 17 (page 38)) provide current state/next state informa-  
tion.  
Table 14: Truth Table – Commands and DQM Operation  
Note 1 applies to all parameters and conditions  
Name (Function)  
CS# RAS# CAS# WE# DQM ADDR  
DQ Notes  
COMMAND INHIBIT (NOP)  
H
L
X
H
L
X
H
H
L
X
H
H
H
L
X
X
X
X
X
NO OPERATION (NOP)  
X
ACTIVE (select bank and activate row)  
READ (select bank and column, and start READ burst)  
WRITE (select bank and column, and start WRITE burst)  
BURST TERMINATE  
L
X
Bank/row  
Bank/col  
X
X
2
3
L
H
H
H
L
L/H  
L/H  
X
L
L
Bank/col Valid  
3
L
H
H
L
L
X
Active  
X
4
PRECHARGE (Deactivate row in bank or banks)  
AUTO REFRESH or SELF REFRESH (enter self refresh mode)  
LOAD MODE REGISTER  
L
L
X
Code  
5
L
L
H
L
X
X
X
6, 7  
8
L
L
L
X
Op-code  
X
Write enable/output enable  
X
X
X
X
X
X
X
X
L
X
X
Active  
High-Z  
9
Write inhibit/output High-Z  
H
9
1. CKE is HIGH for all commands shown except SELF REFRESH.  
Notes:  
2. A[0:n] provide row address (where An is the most significant address bit), BA0 and BA1  
determine which bank is made active.  
3. A[0:i] provide column address (where i = the most significant column address for a given  
device configuration). A10 HIGH enables the auto precharge feature (nonpersistent),  
while A10 LOW disables the auto precharge feature. BA0 and BA1 determine which  
bank is being read from or written to.  
4. The purpose of the BURST TERMINATE command is to stop a data burst, thus the com-  
mand could coincide with data on the bus. However, the DQ column reads a “Don’t  
Care” state to illustrate that the BURST TERMINATE command can occur when there is  
no data present.  
5. A10 LOW: BA0, BA1 determine the bank being precharged. A10 HIGH: all banks pre-  
charged and BA0, BA1 are “Don’t Care.”  
6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW.  
7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” ex-  
cept for CKE.  
8. A[11:0] define the op-code written to the mode register.  
9. Activates or deactivates the DQ during WRITEs (zero-clock delay) and READs (two-clock  
delay).  
COMMAND INHIBIT  
The COMMAND INHIBIT function prevents new commands from being executed by  
the device, regardless of whether the CLK signal is enabled. The device is effectively de-  
selected. Operations already in progress are not affected.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
28  
© 1999 Micron Technology, Inc. All rights reserved.