64Mb: x4, x8, x16 SDRAM
Electrical Specifications – IDD Parameters
–40°C ≤ TA ≤ +105°C (automotive)
3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH
commands, before proper device operation is ensured. (VDD and VDDQ must be powered
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time the tREF refresh requirement is excee-
ded.
4. IDD is dependent on output loading and cycle rates. Specified values are obtained with
minimum cycle time and the outputs open.
5. The IDD current will increase or decrease proportionally according to the amount of fre-
quency alteration for the test condition.
6. Address transitions average one transition every two clocks.
7. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and tCK = 7.5ns; for -6, CL = 3 and tCK =
6ns.
8. Other input signals are allowed to transition no more than once every two clocks and
are otherwise at valid VIH or VIL levels.
9. CKE is HIGH during refresh command period tRFC (MIN) else CKE is LOW. The IDD6 limit is
actually a nominal value and does not result in a fail value.
10. Enables on-chip refresh and address counters.
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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