64Mb: x4, x8, x16 SDRAM
Functional Description
Functional Description
In general, 64Mb SDRAM devices (4 Meg x 4 x 4 banks, 2 Meg x 8 x 4 banks, and 1 Meg x
16 x 4 banks) are quad-bank DRAM that operate at 3.3V and include a synchronous in-
terface. All signals are registered on the positive edge of the clock signal, CLK. Each of
the x4’s 16,777,216-bit banks is organized as 4096 rows by 1024 columns by 4 bits. Each
of the x8’s 16,777,216-bit banks is organized as 4096 rows by 512 columns by 8 bits. Each
of the x16’s 16,777,216-bit banks is organized as 4096 rows by 256 columns by 16 bits.
Read and write accesses to the SDRAM are burst-oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed se-
quence. Accesses begin with the registration of an ACTIVE command, followed by a
READ or WRITE command. The address bits registered coincident with the ACTIVE
command are used to select the bank and row to be accessed (BA0 and BA1 select the
bank, A[11:0] select the row). The address bits (x4: A[9:0]; x8: A[8:0]; x16: A[7:0]) regis-
tered coincident with the READ or WRITE command are used to select the starting col-
umn location for the burst access.
Prior to normal operation, the device must be initialized. The following sections provide
detailed information covering device initialization, register definition, command de-
scriptions, and device operation.
PDF: 09005aef80725c0b
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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