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MT48LC4M16A2P-75G 参数 Datasheet PDF下载

MT48LC4M16A2P-75G图片预览
型号: MT48LC4M16A2P-75G
PDF下载: 下载PDF文件 查看货源
内容描述: SDR SDRAM MT48LC16M4A2 â ????梅格4 ×4× 4银行MT48LC8M8A2 â ???? 2梅格×8× 4银行MT48LC4M16A2 â ???? 1梅格×16× 4银行 [SDR SDRAM MT48LC16M4A2 – 4 Meg x 4 x 4 Banks MT48LC8M8A2 – 2 Meg x 8 x 4 Banks MT48LC4M16A2 – 1 Meg x 16 x 4 Banks]
分类和应用: 动态存储器
文件页数/大小: 83 页 / 3595 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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64Mb: x4, x8, x16 SDRAM  
Electrical Specifications  
Electrical Specifications  
Stresses greater than those listed may cause permanent damage to the device. This is a  
stress rating only, and functional operation of the device at these or any other condi-  
tions above those indicated in the operational sections of this specification is not im-  
plied. Exposure to absolute maximum rating conditions for extended periods may affect  
reliability.  
Table 7: Absolute Maximum Ratings  
Voltage/Temperature  
Symbol  
VDD/VDDQ  
VIN  
Min  
–1  
Max  
4.6  
4.6  
150  
1
Unit  
Voltage on VDD/VDDQ supply relative to VSS  
Voltage on inputs, NC, or I/O balls relative to VSS  
Storage temperature (plastic)  
Power dissipation  
V
–1  
TSTG  
–55  
°C  
W
Table 8: DC Electrical Characteristics and Operating Conditions  
Notes 1–3 apply to all parameters and conditions; VDD/VDDQ = 3.3V ±0.3V  
Parameter/Condition  
Symbol  
VDD, VDDQ  
VIH  
Min  
3
Max  
3.6  
Unit Notes  
Supply voltage  
V
Input high voltage: Logic 1; All inputs  
Input low voltage: Logic 0; All inputs  
Output high voltage: IOUT = –4mA  
Output low voltage: IOUT = 4mA  
Input leakage current:  
2
VDD + 0.3  
V
V
4
4
VIL  
–0.3  
2.4  
0.8  
VOH  
V
VOL  
0.4  
5
V
IL  
–5  
μA  
Any input 0V VIN VDD (All other balls not under test = 0V)  
Output leakage current: DQ are disabled; 0V VOUT VDDQ  
IOZ  
TA  
TA  
TA  
–5  
0
–5  
70  
μA  
˚C  
Operating temperature:  
Commercial  
Industrial  
–40  
–40  
85  
˚C  
Automotive  
105  
˚C  
1. All voltages referenced to VSS.  
Notes:  
2. The minimum specifications are used only to indicate cycle time at which proper opera-  
tion over the full temperature range is ensured; (0°C TA +70°C (commercial), –40°C ≤  
TA +85°C (industrial), and –40°C TA +105°C (automotive)).  
3. An initial pause of 100μs is required after power-up, followed by two AUTO REFRESH  
commands, before proper device operation is ensured. (VDD and VDDQ must be powered  
up simultaneously. VSS and VSSQ must be at same potential.) The two AUTO REFRESH  
command wake-ups should be repeated any time the tREF refresh requirement is excee-  
ded.  
4. VIH overshoot: VIH,max = VDDQ + 2V for a pulse width 3ns, and the pulse width cannot  
be greater than one-third of the cycle rate. VIL undershoot: VIL,min = –2V for a pulse  
width 3ns.  
PDF: 09005aef80725c0b  
64mb_x4x8x16_sdram.pdf - Rev. U 05/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
19  
© 1999 Micron Technology, Inc. All rights reserved.