64Mb: x32
SDRAM
READ – DQM OPERATION 1
T0
T1
T2
T3
T4
T5
T6
T7
T8
t
t
CL
CK
CLK
t
CH
t
t
CKS
CKH
CKE
t
t
CMS
CMH
COMMAND
ACTIVE
NOP
READ
t
NOP
NOP
NOP
NOP
NOP
NOP
t
CMS CMH
DQM 0-3
A0-A9
t
t
AH
AS
2
ROW
COLUMN m
t
t
AH
AS
ENABLE AUTO PRECHARGE
ROW
A10
DISABLE AUTO PRECHARGE
BANK
t
t
AH
AS
BA0, BA1
BANK
t
AC
t
t
t
t
t
OH
AC
OH
AC
OH
DQ
D
OUT
m
DOUT m + 2
D
OUT m + 3
t
LZ
t
t
t
LZ
HZ
HZ
t
RCD
CAS Latency
DON’T CARE
UNDEFINED
TIMING PARAMETERS
-5
-6
-7
-5
-6
-7
SYMBOL* MIN
MAX
MIN
MAX
5.5
MIN
MAX UNITS
SYMBOL* MIN
MAX
MIN
1
MAX
MIN
MAX UNITS
t
t
AC (3)
4.6
5.5
8
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
CKH
1
1.5
1
1
2
1
2
ns
ns
ns
ns
t
t
t
t
t
t
t
t
AC (2)
-
-
7.5
CKS
1.5
1
t
AC (1)
17
17
CMH
CMS
t
AH
AS
1
1.5
2
1
1
2
1.5
1.5
t
t
t
1.5
2.5
2.5
6
HZ (3)
HZ (2)
HZ (1)
4.5
5
5.5
8
ns
ns
ns
ns
ns
ns
CH
2.75
2.75
7
-
-
7.5
17
CL
2
17
t
CK (3)
CK (2)
CK (1)
5
LZ
1
1
2
1
t
t
t
-
10
20
10
OH
1.5
15
2.5
20
t
-
20
RCD
18
*CAS latency indicated in parentheses.
NOTE: 1. For this example, the CAS latency = 2.
2. A8 and A9 = “Don’t Care.”
64Mb: x32 SDRAM
64MSDRAMx32_5.p65 – Rev. B; Pub. 6/02
MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.
©2002,MicronTechnology,Inc.
46
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