512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
WRITE w it h Au t o Pre ch a rg e
1. Interrupted by a READ (with or without auto precharge): A READ to bank m will inter-
rupt a WRITE on bank n when registered, with the data-out appearing CL later. The
t
t
precharge to bank n will begin after WR is met, where WR begins when the READ to
bank m is registered. The last valid WRITE to bank n will be data-in registered one
clock prior to the READ to bank m (Figure 33).
2. Interrupted by a WRITE (with or without auto precharge): A WRITE to bank m will
interrupt a WRITE on bank n when registered. The precharge to bank n will begin
t
t
after WR is met, where WR begins when the WRITE to bank m is registered. The last
valid data WRITE to bank n will be data registered one clock prior to a WRITE to bank
m (Figure 34).
Fig u re 33: WRITE Wit h Au t o Pre ch a rg e In t e rru p t e d b y a READ
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
READ - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
RP - BANK m
Page Active
READ with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
DOUT
DOUT
a
d
d + 1
CL = 3 (bank m)
DON’T CARE
Notes: 1. DQM is LOW.
Fig u re 34: WRITE Wit h Au t o Pre ch a rg e In t e rru p t e d b y a WRITE
T0
T1
T2
T3
T4
T5
T6
T7
CLK
WRITE - AP
BANK n
WRITE - AP
BANK m
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
Page Active
WRITE with Burst of 4
Interrupt Burst, Write-Back
Precharge
BANK n
t
RP - BANK n
t
WR - BANK n
Internal
States
t
WR - BANK m
Write-Back
Page Active
WRITE with Burst of 4
BANK m
BANK n,
COL a
BANK m,
COL d
ADDRESS
DQ
DIN
D
a + 1
IN
D
a + 2
IN
DIN
DIN
DIN
DIN
a
d
d + 1
d + 2
d + 3
DON’T CARE
Notes: 1. DQM is LOW.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
40
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