512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Fig u re 29: Clo ck Su sp e n d Du rin g WRITE Bu rst
T0
T1
T2
T3
T4
T5
CLK
CKE
INTERNAL
CLOCK
NOP
WRITE
NOP
NOP
COMMAND
ADDRESS
BANK,
COL n
D
n
IN
D
n + 1
IN
DIN
n + 2
DIN
DON’T CARE
Notes: 1. For this example, BL = 4 or greater, and DQM is LOW.
Fig u re 30: Clo ck Su sp e n d Du rin g READ Bu rst
T0
T1
T2
T3
T4
T5
T6
CLK
CKE
INTERNAL
CLOCK
READ
NOP
NOP
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
D
OUT
D
OUT
D
n + 2
OUT
DOUT
n + 3
n
n + 1
DON’T CARE
Notes: 1. For this example, CL = 2, BL = 4 or greater, and DQM is LOW.
Bu rst Re a d /Sin g le Writ e
The burst read/ single write mode is entered by programming the write burst mode bit
(M9) in the mode register to a logic 1. In this mode, all WRITE commands result in the
access of a single column location (burst of one), regardless of the programmed BL.
READ commands access columns according to the programmed BL and sequence, just
as in the normal mode of operation.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
37
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