512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
Fig u re 23: WRITE-t o -PRECHARGE
T0
T1
T2
T3
T4
T5
T6
CLK
t
t
WR@ CK ≥ 15ns
DQM
t
RP
NOP
NOP
NOP
WRITE
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
D
n
IN
DIN
n + 1
DQ
t
t
WR@ CK < 15ns
DQM
t
RP
NOP
NOP
WRITE
NOP
NOP
PRECHARGE
ACTIVE
COMMAND
ADDRESS
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
t
WR
D
n
IN
DIN
n + 1
DQ
DON’T CARE
Notes: 1. DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
Fig u re 24: Te rm in a t in g a WRITE Bu rst
T0
T1
T2
CLK
BURST
TERMINATE
NEXT
COMMAND
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
(ADDRESS)
(DATA)
DIN
n
DON’T CARE
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
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