512Mb : 32 Me g x 16, 16 Me g x 32 Mo b ile SDRAM
Op e ra t io n s
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same opera-
tion that would result from the same fixed-length burst with auto precharge. The disad-
vantage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length bursts.
Fig u re 21: Ra n d o m WRITE Cycle s
T0
T1
T2
T3
CLK
WRITE
WRITE
WRITE
WRITE
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL a
BANK,
COL x
BANK,
COL m
D
IN
D
IN
D
IN
DIN
x
m
n
a
DON’T CARE
Notes: 1. Each WRITE command may be to any bank. DQM is LOW.
Fig u re 22: WRITE-t o -READ
T0
T1
T2
T3
T4
T5
CLK
WRITE
NOP
READ
NOP
NOP
NOP
COMMAND
ADDRESS
DQ
BANK,
COL n
BANK,
COL b
DIN
DIN
DOUT
DOUT
b + 1
n
n + 1
b
DON’T CARE
Notes: 1. The WRITE command may be to any bank, and the READ command may be to any bank.
DQM is LOW. CL = 2 for illustration.
PDF: 09005aef81ca5de4/Source: 09005aef81ca5e03
MT48H32M16LF_1.fm - Rev. H 6/07 EN
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2005 Micron Technology, Inc. All rights reserved.
32
MICRON [ MICRON TECHNOLOGY ]
