1Gb: x4, x8, x16 DDR2 SDRAM
Electrical Specifications – IDD Parameters
4. Data bus consists of DQ, DM, DQS, DQS#, RDQS, RDQS#, LDQS, LDQS#, UDQS, and
UDQS#. IDD values must be met with all combinations of EMR bits 10 and 11.
5. Definitions for IDD conditions:
LOW
VIN ≤ VIL(AC)max
HIGH
Stable
VIN ≥ VIH(AC)min
Inputs stable at a HIGH or LOW level
Floating Inputs at VREF = VDDQ/2
Switching Inputs changing between HIGH and LOW every other clock cycle (once per
two clocks) for address and control signals
Switching Inputs changing between HIGH and LOW every other data transfer (once
per clock) for DQ signals, not including masks or strobes
6. IDD1, IDD4R, and IDD7 require A12 in EMR to be enabled during testing.
7. The following IDD values must be derated (IDD limits increase) on IT-option and AT-op-
tion devices when operated outside of the range 0°C ≤ TC ≤ 85°C:
When
TC ≤ 0°C
IDD2P and IDD3P(SLOW) must be derated by 4%; IDD4R and IDD5W must be derat-
ed by 2%; and IDD6 and IDD7 must be derated by 7%
When
TC ≥ 85°C
IDD0, IDD1, IDD2N, IDD2Q, IDD3N, IDD3P(FAST), IDD4R, IDD4W, and IDD5W must be derat-
ed by 2%; IDD2P must be derated by 20%; IDD3P(SLOW) must be derated by
30%; and IDD6 must be derated by 80% (IDD6 will increase by this amount if
TC < 85°C and the 2X refresh option is still enabled)
PDF: 09005aef821ae8bf
1GbDDR2.pdf – Rev. T 02/10 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
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