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MT41J256M4 参数 Datasheet PDF下载

MT41J256M4图片预览
型号: MT41J256M4
PDF下载: 下载PDF文件 查看货源
内容描述: DDR3 SDRAM MT41J256M4 â ????梅格32 ×4× 8银行MT41J128M8 â ????梅格16 ×8× 8银行MT41J64M16 â ???? 8梅格×16× 8银行 [DDR3 SDRAM MT41J256M4 – 32 Meg x 4 x 8 banks MT41J128M8 – 16 Meg x 8 x 8 banks MT41J64M16 – 8 Meg x 16 x 8 banks]
分类和应用: 动态存储器双倍数据速率
文件页数/大小: 214 页 / 2938 K
品牌: MICRON [ MICRON TECHNOLOGY ]
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1Gb: x4, x8, x16 DDR3 SDRAM  
Electrical Specifications – DC and AC  
Table 27: Differential Input Operating Conditions (CK, CK# and DQS, DQS#)  
Parameter/Condition  
Symbol  
VIH,diff  
Min  
200  
Max  
n/a  
Unit Notes  
Differential input voltage logic high - slew  
Differential input voltage logic low - slew  
Differential input voltage logic high  
Differential input voltage logic low  
mV  
mV  
mV  
mV  
mV  
4
4
VIL,diff  
n/a  
–200  
VIH,diff(AC)  
VIL,diff(AC)  
VIX  
2 × (VIH(AC) - VREF  
)
VDD/VDDQ  
2 × (VIL(AC)-VREF  
VREF(DC) + 150  
5
VSS/VSSQ  
)
6
Differential input crossing voltage relative  
to VDD/2 for DQS, DQS#; CK, CK#  
VREF(DC) - 150  
4, 7  
Differential input crossing voltage relative  
to VDD/2 for CK, CK#  
VIX (175)  
VSEH  
VREF(DC) - 175  
VREF(DC) + 175  
mV  
4, 7, 8  
Single-ended high level for strobes  
Single-ended high level for CK, CK#  
Single-ended low level for strobes  
Single-ended low level for CK, CK#  
VDDQ/2 + 175  
VDD/2 + 175  
VSSQ  
VDDQ  
VDD  
mV  
mV  
mV  
mV  
5
5
6
6
VSEL  
VDDQ/2 - 175  
VDD/2 - 175  
VSS  
1. Clock is referenced to VDD and VSS. Data strobe is referenced to VDDQ and VSSQ  
2. Reference is VREFCA(DC) for clock and VREFDQ(DC) for strobe.  
3. Differential input slew rate = 2 V/ns  
.
Notes:  
4. Defines slew rate reference points, relative to input crossing voltages.  
5. Minimum DC limit is relative to single-ended signals; overshoot specifications are appli-  
cable.  
6. Maximum DC limit is relative to single-ended signals; undershoot specifications are ap-  
plicable.  
7. The typical value of VIX(AC) is expected to be about 0.5 × VDD of the transmitting device,  
and VIX(AC) is expected to track variations in VDD. VIX(AC) indicates the voltage at which  
differential input signals must cross.  
8. The VIX extended range ( 175mV) is allowed only for the clock; this VIX extended range  
is only allowed when the following conditions are met: The single-ended input signals  
are monotonic, have the single-ended swing VSEL, VSEH of at least VDD/2 250mV, and  
the differential slew rate of CK, CK# is greater than 3 V/ns.  
9. VIX must provide 25mV (single-ended) of the voltages separation.  
PDF: 09005aef826aa906  
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN  
Micron Technology, Inc. reserves the right to change products or specifications without notice.  
51  
‹ 2006 Micron Technology, Inc. All rights reserved.  
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