1Gb: x4, x8, x16 DDR3 SDRAM
Dynamic ODT
• During DRAM operation without READ or WRITE commands, the termination is con-
trolled.
– Nominal termination strength RTT,nom is used.
– Termination on/off timing is controlled via the ODT ball and latencies ODTLon and
ODTLoff.
• When a WRITE command (WR, WRAP, WRS4, WRS8, WRAPS4, WRAPS8) is registered,
and if dynamic ODT is enabled, the ODT termination is controlled.
– A latency of ODTLcnw after the WRITE command: termination strength RTT,nom
switches to RTT(WR)
– A latency of ODTLcwn8 (for BL8, fixed or OTF) or ODTLcwn4 (for BC4, fixed or OTF)
after the WRITE command: termination strength RTT(WR) switches back to RTT,nom
.
– On/off termination timing is controlled via the ODT ball and determined by ODT-
Lon, ODTLoff, ODTH4, and ODTH8.
– During the tADC transition window, the value of RTT is undefined.
ODT is constrained during writes and when dynamic ODT is enabled (see Table 86
(page 196)). ODT timings listed in Table 84 (page 194) also apply to dynamic ODT
mode.
Table 86: Dynamic ODT Specific Parameters
Definition for All
Symbol
Description
Begins at
Defined to
DDR3 Speed Bins Unit
ODTLcnw
Change from RTT,nom to
RTT(WR)
Write registration RTT switched from RTT,nom
to RTT(WR)
WL - 2
tCK
tCK
tCK
tCK
ODTLcwn4
ODTLcwn8
tADC
Change from RTT(WR) to
Write registration
RTT switched from RTT(WR)
to RTT,nom
4tCK + ODTL off
6tCK + ODTL off
0.5tCK 0.2tCK
R
TT,nom (BC4)
Change from RTT(WR) to
TT,nom (BL8)
RTT change skew
Write registration
RTT switched from RTT(WR)
to RTT,nom
R
ODTLcnw completed RTT transition complete
Table 87: Mode Registers for RTT,nom
MR1 (RTT,nom
)
M9
0
M6
0
M2
0
RTT,nom (RZQ)
Off
RTT,nom (Ohm)
RTT,nom Mode Restriction
Off
60
n/a
0
0
1
RZQ/4
Self refresh
0
1
0
RZQ/2
120
0
1
1
RZQ/6
40
1
0
0
RZQ/12
RZQ/8
20
Self refresh, write
1
0
1
30
1
1
0
Reserved
Reserved
Reserved
Reserved
n/a
n/a
1
1
1
1. RZQ = 240Ω. If RTT,nom is used during WRITEs, only RZQ/2, RZQ/4, RZQ/6 are allowed.
Note:
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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196
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