Figure 110: Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
T12
T13
T14
T15
T16
T17
CK#
CK
Command
NOP
NOP
NOP
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
Address
ODTH4
ODTLoff
ODTH4
ODT
RTT
ODTLon
ODTLcwn4
tADC (MIN)
tAON (MIN)
tADC (MIN)
tADC (MAX)
tAOF (MIN)
tAOF (MAX)
RTT(WR)
RTT,nom
RTT,nom
tAON (MAX)
ODTLcnw
tADC (MAX)
DQS, DQS#
DQ
DI
n
DI
DI
DI
n + 1 n + 2 n + 3
WL
Transitioning
Don’t Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
Notes:
2. ODTH4 applies to first registering ODT HIGH and then to the registration of the WRITE command. In this example,
ODTH4 is satisfied if ODT goes LOW at T8 (four clocks after the WRITE command).
Figure 111: Dynamic ODT: Without WRITE Command
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
Command
Address
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
ODTH4
ODTLoff
ODTLon
ODT
RTT
t
t
AON (MAX)
AOF (MIN)
RTT,nom
t
AON (MIN)
t
AOF (MAX)
DQS, DQS#
DQ
Transitioning
Don’t Care
1. AL = 0, CWL = 5. RTT,nom is enabled and RTT(WR) is either enabled or disabled.
Notes:
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW; in this example, ODTH4 is satisfied. ODT reg-
istered LOW at T5 is also legal.
MICRON [ MICRON TECHNOLOGY ]
