1Gb: x4, x8, x16 DDR3 SDRAM
Dynamic ODT
Figure 113: Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
Command
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
Address
ODTH4
ODTLoff
ODT
ODTLon
tADC (MAX)
tAON (MIN)
tAOF (MIN)
tAOF (MAX)
tADC (MIN)
R
R
R
TT,nom
TT(WR)
TT
tADC (MAX)
ODTLcwn4
DQS, DQS#
DQ
DI
n
DI
DI
DI
n + 1 n + 2 n + 3
WL
Transitioning
Don’t Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom and RTT(WR) are enabled.
Notes:
2. ODTH4 is defined from ODT registered HIGH to ODT registered LOW, so in this example,
ODTH4 is satisfied. ODT registered LOW at T5 is also legal.
Figure 114: Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
T0
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
T11
CK#
CK
Command
NOP
WRS4
Valid
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
ODTLcnw
Address
ODTLoff
ODTH4
ODT
RTT
t
t
ADC (MAX)
AOF (MIN)
ODTLon
R
TT(WR)
t
t
AON (MIN)
ODTLcwn4
AOF (MAX)
DQS, DQS#
DQ
WL
DI
DI
DI
DI
n
n + 1 n + 2 n + 3
Transitioning
Don’t Care
1. Via MRS or OTF. AL = 0, CWL = 5. RTT,nom can be either enabled or disabled. If disabled,
ODT can remain HIGH. RTT(WR) is enabled.
Notes:
2. In this example ODTH4 = 4 is satisfied exactly.
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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