1Gb: x4, x8, x16 DDR3 SDRAM
RESET Operation
Figure 108: RESET Sequence
System RESET
(warm boot)
Stable and
valid clock
Tc0
Td0
Tb0
T1
T0
Ta0
tCK
CK#
CK
tCL
tCL
t CKSRX1
T = 100ns (MIN)
tIOZ = 20ns
RESET#
tIS
tIS
T = 10ns (MIN)
Valid
CKE
tIS
Static LOW in case RTT_Nom is enabled at time Ta0, otherwise static High or Low
Valid
Valid
ZQCL
Valid
Valid
ODT
tIS
Command
DM
MRS
MRS
MRS
MRS
NOP
Address
A10
Code
Code
Code
Code
Code
Code
Code
Valid
Valid
Valid
Code
A10 = H
BA0 = L
BA1 = H
BA2 = L
BA0 = H
BA1 = H
BA2 = L
BA0 = H
BA1 = L
BA2 = L
BA0 = L
BA1 = L
BA2 = L
BA[2:0]
High-Z
High-Z
DQS
DQ
High-Z
RTT
tMRD
tMRD
tXPR
tMRD
tMOD
T = 500μs (MIN)
MR0 with
DLL RESET
MR1 with
DLL ENABLE
MR2
MR3
ZQCAL
tDLLK
All voltage
supplies valid
and stable
tZQinit
DRAM ready
for external
commands
Normal
operation
Indicates break
in time scale
Don’t Care
1. The minimum time required is the longer of 10ns or 5 clocks.
Note:
PDF: 09005aef826aa906
1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
Micron Technology, Inc. reserves the right to change products or specifications without notice.
192
2006 Micron Technology, Inc. All rights reserved.
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