1Gb: x4, x8, x16 DDR3 SDRAM
Dynamic ODT
Table 88: Mode Registers for RTT(WR)
MR2 (RTT(WR)
M10
)
M9
0
RTT(WR) (RZQ)
RTT(WR) (Ohm)
0
0
1
1
Dynamic ODT off: WRITE does not affect RTT,nom
1
RZQ/4
RZQ/2
60
120
0
1
Reserved
Reserved
Table 89: Timing Diagrams for Dynamic ODT
Figure and Page
Title
Figure 110 (page 198)
Figure 111 (page 198)
Figure 112 (page 199)
Figure 113 (page 200)
Figure 114 (page 200)
Dynamic ODT: ODT Asserted Before and After the WRITE, BC4
Dynamic ODT: Without WRITE Command
Dynamic ODT: ODT Pin Asserted Together with WRITE Command for 6 Clock Cycles, BL8
Dynamic ODT: ODT Pin Asserted with WRITE Command for 6 Clock Cycles, BC4
Dynamic ODT: ODT Pin Asserted with WRITE Command for 4 Clock Cycles, BC4
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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