1Gb: x4, x8, x16 DDR3 SDRAM
On-Die Termination (ODT)
Table 83: Truth Table – ODT (Nominal)
Note 1 applies to the entire table
MR1[9, 6, 2]
000
ODT Pin
DRAM Termination State
RTT,nom disabled, ODT off
RTT,nom disabled, ODT on
RTT,nom enabled, ODT off
RTT,nom enabled, ODT on
RTT,nom reserved, ODT on or off
DRAM State
Any valid
Notes
0
1
0
1
X
2
3
2
3
000
Any valid except self refresh, read
Any valid
000–101
000–101
110 and 111
Any valid except self refresh, read
Illegal
1. Assumes dynamic ODT is disabled (see Dynamic ODT (page 195) when enabled).
Notes:
2. ODT is enabled and active during most writes for proper termination, but it is not illegal
for it to be off during writes.
3. ODT must be disabled during reads. The RTT,nom value is restricted during writes. Dynam-
ic ODT is applicable if enabled.
Nominal ODT resistance RTT,nom is defined by MR1[9, 6, 2], as shown in Mode Register 1
(MR1) Definition. The RTT,nom termination value applies to the output pins previously
mentioned. DDR3 SDRAM supports multiple RTT,nom values based on RZQ/n where n
can be 2, 4, 6, 8, or 12 and RZQ is 24±Ω. RTT,nom termination is allowed any time after the
DRAM is initialized, calibrated, and not performing read access, or when it is not in self
refresh mode.
Write accesses use RTT,nom if dynamic ODT (RTT(WR)) is disabled. If RTT,nom is used dur-
ing writes, only RZQ/2, RZQ/4, and RZQ/6 are allowed (see Table 80 (page 196)). ODT
timings are summarized in Table 84 (page 194), as well as listed in Table 56 (page 09).
Examples of nominal ODT timing are shown in conjunction with the synchronous
mode of operation in Synchronous ODT Mode (page 2±1).
Table 84: ODT Parameters
Definition for All
DDR3 Speed Bins
Symbol
ODTLon
ODTLoff
tAONPD
tAOFPD
ODTH4
Description
Begins at
Defined to
Unit
tCK
tCK
ns
ODT synchronous turn-on delay
ODT synchronous turn-off delay
ODT asynchronous turn-on delay
ODT asynchronous turn-off delay
ODT registered HIGH RTT(ON) tAON
ODT registered HIGH RTT(OFF) tAOF
CWL + AL - 2
CWL + AL - 2
2–8.5
ODT registered HIGH
ODT registered HIGH
RTT(ON)
RTT(OFF)
2–8.5
4tCK
ns
tCK
ODT minimum HIGH time after ODT ODT registered HIGH ODT registered
assertion or write (BC4)
or write registration
with ODT HIGH
LOW
ODTH8
tAON
tAOF
ODT minimum HIGH time after
write (BL8)
Write registration
with ODT HIGH
ODT registered
LOW
6tCK
tCK
ps
ODT turn-on relative to ODTLon
completion
Completion of
ODTLon
RTT(ON)
See Table 56 (page 79)
0.5tCK 0.2tCK
ODT turn-off relative to ODTLoff
completion
Completion of
ODTLoff
RTT(OFF)
tCK
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1Gb_DDR3_SDRAM.pdf - Rev. L 03/13 EN
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194
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